1. Field of the Invention
The present invention relates to a semiconductor memory device such as electrically erasable programmable ROM (EEPROM) and a method of manufacturing the same.
2. Description of the Related Art
In recent years, there has been much activity in development of electrically programmable-erasable non-volatile memory devices such as EPROMs or flash memory devices. A low cost and high density flash memory device is currently in great demand. Among flash memories, a flash memory in which both writing and erasing are performed by using the Fouler Nordheim (F-N) tunneling effect has various advantages compared with another type flash memory.
For example, this type of device can improve writing speed with inner booster circuit due to the small power consumption than channel hot electron (CHE) injection type devices.
It is well known that as to endurance of writing cycles the F-N tunneling over the entire area of the channel region has advantage in both writing and erasing.
In a device which write data by extracting electrons from a control gate using the F-N tunneling, it suffers from the disadvantage of low writing speed with the inner circuit due to tunnel current when writing data.
However, a flash memory described above requires a high voltage of about 20V when writing, so that it suffers from the disadvantage that it is hard to ensure withstand voltage for inversion and for punch-through in the isolation area between memory cells next to each other along a bit line.
In the case of isolation of a LOCOS and the like, if the thickness of the LOCOS would be thicker to ensure higher withstand voltage for inversion, isolation width would be wider because the LOCOS is thicker, the birds-beak is wider, so that the integration of large numbers of devices in a small area is more difficult.
It is possible to use trench isolation instead of LOCOS. But, to form trench isolation having both wide widths and narrow widths, it requires complex burying and planalization processes such as chemical mechanical planarization (CMP), so there is a problem of increased manufacturing costs.
Further, it is possible to form a more heavily doped channel stop. But, to ensure proper junction voltage, an isolation area between the source-drain region and the channel stop ion implantation region is required, so it would degrade the ability to have higher density.